1. Field of the Invention
The present invention relates to an image processing apparatus having functions of A-D conversion and D-A conversion, and more specifically pertains to a technique of processing high-frequency image signals.
2. Discussion of the Background
With recent advance in video technology, image signals processed by an image processing apparatus tend to have higher frequency. The higher frequency of image signals requires higher operating frequencies of an analog-to-digital conversion (hereinafter referred to as xe2x80x98A-D conversionxe2x80x99) unit and a digital-to-analog conversion (hereinafter referred to as xe2x80x98D-A conversionxe2x80x99) unit.
Since there is a limit of enhancing the operating frequencies of the A-D converter and D-A converter, however, it is difficult to carry out A-D conversion and D-A conversion of high-frequency image signals.
The object of the present invention is thus to solve the above problem of the prior art and provide a technique that facilitates A-D conversion and D-A conversion of high-frequency image signals.
At least part of the above and the other related objects is attained by a first image processing apparatus of the present invention, which includes: a first sampling clock generator that generates Nw first sampling clock signals, which respectively have a first frequency that is synchronous with a first synchronizing signal of a given first analog image signal and phases that are sequentially shifted; and an A-D conversion unit that converts the first analog image signal with respect to Nw pixels into Nw digital image signals, wherein the A-D conversion unit has Nw A-D converters, which commonly receive the first analog image signal and successively carry out A-D conversion of the first analog image signal in response to the Nw first sampling clock signals having the sequentially shifted phases, thereby generating the Nw digital image signals with respect to the Nw pixels, the Nw digital image signals having phases sequentially shifted.
In the above image processing apparatus, since each of the Nw A-D converters carries out A-D conversion at the relatively low first frequency, the input analog image signal having the high frequency can be readily converted to digital image signals.
In accordance with one preferable application of the first image processing apparatus, the first sampling clock generator includes: a first original sampling clock generation circuit that generates a first original sampling clock signal having the first frequency, in response to the first synchronizing signal; and a first sampling clock generation circuit that generates the Nw first sampling clock signals having the sequentially shifted phases, in response to the first original sampling clock signal.
This structure generates the original sampling clock signal, which is synchronous with the synchronizing signal of the analog image signal, in order to facilitate generation of the Nw first sampling clock signals that are synchronous with the synchronizing signal and have the sequentially shifted phases.
In the first image processing apparatus of this structure, it is preferable that the first sampling clock generation circuit initializes the Nw first sampling clock signals having the sequentially shifted phases, in response to a pulse of the first synchronizing signal, so that a fixed phase relationship is attained between the first synchronizing signal and each of the Nw first sampling clock signals having the sequentially shifted phases.
This arrangement enables the Nw first sampling clock signals to respectively hold the fixed phase relations to the synchronizing signal of the analog image signal. Accordingly each of the pixels arranged in time series and included between the pulses of the synchronizing signal of the analog image signal undergoes A-D conversion at a fixed phase.
In the first image processing apparatus discussed above, it is preferable that the first sampling clock generation circuit includes: a first PLL circuit that generates a first dot clock signal having a second frequency suitable for sampling the first analog image signal, in response to the first original sampling clock signal, the second frequency being Nw times the first frequency; and a first sampling clock extraction circuit that extracts the Nw first sampling clock signals, which have the first frequency and the phases sequentially shifted by a period of the first dot clock signal, in response to the first dot clock signal.
The generation of the dot clock signal having the second frequency, which is Nw times the first frequency, facilitates generation of the Nw first sampling clock signals that are suitable for A-D conversion in the Nw A-D converters.
In the first image processing apparatus discussed above, it is also preferable that the first sampling clock generation circuit includes: a first delay clock generation circuit that sequentially delays the first original sampling clock signal to generate the Nw first sampling clock signals having the sequentially shifted phases.
This structure generates the Nw first sampling clock signals without generating the dot clock signal having the relatively high second frequency. The advantage of this structure is that transfer of high-frequency signals is not required through wiring between the respective circuits when the circuits are mounted on a printed board.
In accordance with one preferable application, the first image processing apparatus having any one of the above structures further includes: an image memory that stores digital image signals; and a write control unit that writes the Nw digital image signals output from the A-D conversion unit into continuous storage areas in the image memory.
The write control unit writes the Nw digital image signals with respect to the Nw pixels into the consecutive storage areas of the image memory, so that the digital image signals are stored in the sequence of the original pixel array.
In accordance with another preferable application of the first image processing apparatus having any one of the above structures, the first sampling clock generator includes: a second sampling clock generation circuit that generates Nw second sampling clock signals, which have sequentially shifted phases and maintain fixed phase relations respectively to the Nw first sampling clock signals having the sequentially shifted phases, wherein the A-D conversion unit further includes Nw latch circuits that latch and output the Nw digital image signals, which are output from the Nw A-D converters and have the sequentially shifted phases, in response to the Nw second sampling clock signals having the sequentially shifted phases.
In this structure, the A-D conversion unit outputs the Nw digital image signals, which are output from the Nw A-D converters and have the sequentially shifted phases, in response to the second sampling clock signals that hold the fixed phase relations to the first sampling clock signals.
In the first image processing apparatus of this structure, the write control unit receives the Nw digital image signals supplied from the A-D conversion unit and at least one of the Nw second sampling clock signals, which are supplied from the first sampling clock generator and have the sequentially shifted phases.
This structure enables the write control unit to utilize the signal that is synchronous with the digital image signals output from the A-D converters. This effectively prevents the write control unit from sampling the digital image signals at transitional periods of the data, thereby ensuring sampling of the digital image signals.
In accordance with one preferable application of the first image processing apparatus discussed above, the write control unit includes plural stages of digital image signal phase regulation circuits that cause the Nw digital image signals, which have the sequentially shifted phases and are supplied from the A-D conversion unit, to be output in an identical phase. The plural stages of digital image signal phase regulation circuits have a hierarchical structure, in which a number of circuits included in each stage gradually decreases towards a last stage. A plurality of digital image signal phase regulation circuits included in each stage, except the last stage, latch a plurality of input digital image signals in fixed phases, which are different from one another, and supply the latched digital image signals to digital image signal phase regulation circuits included in a next stage. A digital image signal phase regulation circuit included in the last stage latches the Nw digital image signals supplied from a previous stage in an identical phase.
This arrangement enables the digital image signal phase regulation circuits included in each stage to carry out sampling at relatively marginal timings, so that the Nw digital image signals having the sequentially shifted phases can be changed readily to the digital image signals of an identical phase.
The first image processing apparatus discussed above may further include: a first switching circuit that supplies at least part of the Nw first sampling clock signals having the sequentially shifted phases to arbitrary A-D converters selected among the Nw A-D converters; and a second switching circuit that supplies at least part of the Nw second sampling clock signals having the sequentially shifted phases to selected latch circuits among the Nw latch circuits, the selected latch circuits corresponding to the arbitrary A-D converters to which the first sampling clock signals are supplied by the first switching circuit.
This structure supplies the first and the second sampling clock signals to the arbitrary A-D converters and the latch circuits, and thereby enables the Nw A-D converters and Nw latch circuits to be activated in an arbitrary sequence.
In accordance with one preferable application of the first image processing apparatus having any one of the above structures, the first sampling clock generator and the A-D conversion unit are integrated into one chip.
Such integration reduces the possibility of incorrect operation in the case of processing the signals of relatively high frequency.
The present invention is also directed to a second image processing apparatus, which includes: a second sampling clock generator that generates Nr third sampling clock signals, which respectively have a third frequency that is synchronous with a second synchronizing signal of a second analog image signal to be output and phases that are sequentially shifted; Nr D-A converters that receive digital image signals with respect to Nr pixels in parallel, carry out D-A conversion of the digital image signals with respect to the Nr pixels, in response to the Nr third sampling clock signals having the sequentially shifted phases, thereby generating Nr partial analog image signals having sequentially shifted phases; and a video switch that successively selects the Nr partial analog image signals output from the Nr D-A converters, so as to generate the second analog image signal.
In the second image processing apparatus, since each of the Nr D-A converters carries out D-A conversion at the relatively low third frequency, the digital images signals can be readily converted to the output analog image signal having the high frequency.
The present invention is further directed to a third image processing apparatus, which includes: an A-D conversion unit having Mw A-D converters (where Mw is an integer of not less than 2), into which a given first analog image signal is commonly input; a first sampling clock generator that generates Nw first sampling clock signals (where Nr is an integer of not less than 1 and not greater than Mw and denotes a working number of A-D converters actually used), which respectively have a first frequency that is synchronous with a first synchronizing signal of the first analog image signal and phases that are sequentially shifted; and a write control signal regulation unit that halts operation of unused (Mwxe2x88x92Nw) A-D converters according to the working number Nw of the A-D converters, controls operation of the first sampling clock generator according to the working number Nw, and causes the Nw A-D converters to successively carry out A-D conversion of the first analog image signal in response to the Nw first sampling clock signals having the sequentially shifted phases, thereby generating digital image signals with respect to Nw pixels.
The third image processing apparatus has the same functions and effects as those of the first image processing apparatus. Additional advantage of the third image processing apparatus is to reduce the power consumption by regulating the working number Nw of the A-D converters according to the frequency of the first analog image signal.
The present invention is also directed to a fourth image processing apparatus, which includes: Mr D-A converters (where Mr is an integer of not less than 2); a second sampling clock generator that generates Nr third sampling clock signals (where Nr is an integer of not less than 1 and not greater than Mr and denotes a working number of D-A converters actually used), which respectively have a third frequency that is synchronous with a second synchronizing signal of a second analog image signal to be output and phases that are sequentially shifted; a read control signal regulation unit that halts operation of unused (Mrxe2x88x92Nr) D-A converters according to the working number Nr of the D-A converters, controls operation of the second sampling clock generator according to the working number Nr, and causes the Nr D-A converters to successively carry out D-A conversion of digital image signals with respect to Nr pixels, in response to the Nr third sampling clock signals having the sequentially shifted phases, thereby generating Nr partial analog image signals that have phases sequentially shifted; and a video switch that successively selects the Nr partial analog image signals output from the Nr D-A converters, so as to generate the second analog image signal.
The fourth image processing apparatus has the same functions and effects as those of the second image processing apparatus. Additional advantage of the fourth image processing apparatus is to reduce the power consumption by regulating the working number Nr of the D-A converters according to the frequency of the second analog image signal.
Each of the first and the third image processing apparatuses may further include a phase regulation circuit that generates an external sampling clock signal from the first original sampling clock signal, the external sampling clock signal having an identical period to that of the first original sampling clock signal and a phase suitable for processing the Nw digital image signals.
In the image processing apparatus of this structure, the phase regulation circuit generates the external sampling clock signal, which has the phase suitable for processing the Nw digital image signals. Accordingly the suitable sampling clock signal can be supplied to a subsequent circuit, when the delay of data after the A-D conversion gives a significant influence on the subsequent circuit.
In accordance with one preferable application of the first image processing apparatus, the Nw A-D converters are provided for each of plural color signals representing a color image, and the Nw A-D converters for each color signal are integrated into a separate integrated circuit.
In this image processing apparatus, since the Nw A-D converters are integrated for each color signal, the reference voltage for regulating a variation intrinsic to the A-D converters can be set common to the A-D converters of one-chip configuration, thereby effectively reducing a variation in luminance among the pixels with respect to each color.
In accordance with one preferable application of the second image processing apparatus, the Nr D-A converters are provided for each of plural color signals representing a color image, and the Nr D-A converters for each color signal are integrated into a separate integrated circuit.
In this image processing apparatus, since the Nr D-A converters are integrated for each color signal, the reference voltage for regulating a variation intrinsic to the D-A converters can be set common to the D-A converters of one-chip configuration, thereby effectively reducing a variation in luminance among the pixels with respect to each color.
In accordance with one preferable application of the third image processing apparatus, the Mw A-D converters are provided for each of plural color signals representing a color image, and the Mw A-D converters for each color signal are integrated into a separate integrated circuit.
In this image processing apparatus, since the Mw A-D converters are integrated for each color signal, the reference voltage for regulating a variation intrinsic to the A-D converters can be set common to the A-D converters of one-chip configuration, thereby effectively reducing a variation in luminance among the pixels with respect to each color.
In accordance with one preferable application of the fourth image processing apparatus, the Mr D-A converters are provided for each of plural color signals representing a color image, and the Mr D-A converters for each color signal are integrated into a separate integrated circuit.
In this image processing apparatus, since the Mr D-A converters are integrated for each color signal, the reference voltage for regulating a variation intrinsic to the D-A converters can be set common to the D-A converters of one-chip configuration, thereby effectively reducing a variation in luminance among the pixels with respect to each color.
The present invention is also directed to an image display apparatus, which includes any one of the first through the fourth image processing apparatuses; and a display unit that displays an image processed by the image processing apparatus.
This arrangement enables the image processed by one of the first through the fourth image processing apparatuses to be displayed on the display unit, such as a liquid-crystal panel.
There are a variety of other aspects of the present invention as discussed below.
A first aspect is a recording medium, on which a computer program for causing a computer to carry out at least part of the respective steps or the respective units of the present invention is recorded. Available examples of the recording media include flexible disks, CD-ROMs, magneto-optic discs, punched cards, prints with barcodes or other codes printed thereon, internal storage devices (memories like RAM and ROM) and external storage devices of the computer, and a variety of other computer readable media.
A second aspect is a program supply apparatus that supplies a computer program for causing the computer to carry out at least part of the respective steps or the respective units of the present invention, via a communication path.